1. Technical Field
The present invention relates to a network interface for transferring constant bit rate (CBR) data, e.g. voice and real-time data between an Asynchronous Transfer Mode (ATM) network and a Plesiochronous Digital Hierarchy (PDH) network, and more specifically, relates to a network interface between an ATM network and a PDH network for handling four different types of services such as connecting the ATM network by the PDH primary rate (T1/E1) of 1.544 Mbps (T1) rate, 2.048 Mbps (E1) rate, T1 channelized (64 kbpsxc3x9724 time slots) data and E1 channelized (64 kbpsxc3x9730 time slots or 64 kbpsxc3x9731 time slots) data.
2. Related Art
Generally, ATM is a specific packet-oriented transfer mode using an asynchronous time division multiplexing technique where both line switching and packet switching are unified and many pieces of data information such as voice, video, and data are organized in fixed-sized packets, called cells each comprised of a data portion and a header portion for storing destination information needed to route the cell through the network at a constant bit rate (CBR). The operation of ATM networks is well known and therefore, need not be described herein. A network interface is required to permit the ATM network to interface with another ATM network or different types of existing signaling networks such as disclosed in U.S. Pat. No. 5,274,768 for High-Performance Host Interface For ATM Networks issued to Traw et al., U.S. Pat. No. 5,450,411 for Network Interface For Multiplexing And Demultiplexing Isochronous And Bursty Data Streams In ATM Networks issued to Heil, U.S. Pat. No. 5,483,527 for Terminal Adapter For Interfacing An ATM Network With A STM Network issued to Doshi et al., U.S. Pat. No. 5,524,113 for ATM Switch Interface issued to Gaddis, U.S. Pat. No. 5,606,559 for System And Method For An Efficient ATM Adapter/Device Driver Interface issued to Badgeret al., U.S. Pat. No. 5,619,500 for ATM Network Interface issued to Hiekali, U.S. Pat. No. 5,689,512 for ATM Cell Interface And Method For Dispatching An ATM Cell issued to Bitz et al., and U.S. Pat. No. 5,706,285 for Network Interfacing Method And A Network Interface For A Digital Transmission Network issued to Saijonmaa et al., and U.S. Pat. No. 5,771,350 for Asynchronous Transfer Mode (ATM) Network Adaptor For The Simultaneous Processing Of The Multi-Channel Traffic issued to Won.
ATM network may also be crossed connected with a plesiochronous digital hierarchy (PDH) a network in the manner disclosed, for example, in U.S. Pat. No. 5,577,039 for System And Method Of Signal Transmission Within A Plesiochronous Digital Hierarchy unit Using ATM Adaptation Layers issued to Won et al., and assigned to the assignee of the instant application. Generally, PDH network users who receive T1 or E1 transfer service through a private automatic branch exchange (PABX) are supported by ATM network. However, an interface of PDH network is different from that of ATM network. Accordingly, a matching interface module is needed. A printed circuit board (PCB) is typically used to perform a single interface function between an ATM network and a PDH network. Since the ATM network and the PDH network support four different services such as connecting the ATM network by the PDH primary rate (T1/E1) of 1.544 Mbps data rate for T1 lines, and 2.048 Mbps data rate for E1 lines, T1 channelized (64 kbpsxc3x9724 time slots) data and E1 channelized (64 kbpsxc3x9730 time slots or 64 kbpsxc3x9731 time slots) data, four different types of printed circuit boards (PCB) are needed for interfacing the ATM network and the PDH network. The users must purchase no other printed circuit board (PCB) but the one intended to support the service, and the printed circuit board (PCB) is not useful when the service type is changed. The users must then purchase another printed circuit board (PCB) according to the channel characteristics of 1.544 Mbps (T1) rate, 2.048 Mbps (E1) rate, 64 kbps time slotized channel, and 64 kbps time slotized E1.
Accordingly, it is therefore an object of the present invention to provide a network interface for interfacing an asynchronous transfer mode (ATM) network and a plesiochronous digital hierarchy (PDH) network.
It is also an object to provide a single interface module for supporting four different types of services for PDH network subscribers using an ATM network.
It is an another object to provide a network interface of an ATM network and a PDH network for supporting four different types of primary rates such as T1 (1.544 Mbps), E1 (2.048 Mbps), T1 channelized (64 kbpsxc3x9724 time slots) data, E1 channelized (64 kbpsxc3x9730 time slots, or 64 kbpsxc3x9731 time slots) data, and enabling the ATM network and the PDH network to work together using an interface control signal generated according to the characteristics of the PDH network.
These and other objects of the present invention can be achieved by a network interface for providing an interface between an ATM network and a PDH network which comprises a line interface unit (LIU) for interfacing between the ATM network and the PDH network such that when ATM network receives data from PDH network, the line interface unit receives bipolar analog data of T1 or E1 and provides a receiving clock of T1 or E1, and PDH digital data, and when PDH network receives data from ATM network, the line interface unit receives the PDH digital data and provides primary bipolar analog data of T1 or E1. A framer is connected to the line interface unit for framing the received multiple T1/E1 channelized data of PDH network to generate frames and provide T1/E1 PDH data in a T1 or E1 unchannelized mode, and provide synchronization information and signaling information of 64 kbpsxc3x97n (n=30 or 31) service. An interface controller which, in the T1 channelized and E1 channelized mode, receives and revises the synchronization information and signaling information to distinguish time slot from the framer, and provides an interface signal which is the information of frame overhead. An AAL1-SAR device which divides ATM cell into PDH data stream or reassembles PDH data stream into ATM cell, and services PCM transfer data which have the characteristics of CBR (Constant Bit Rate) of PDH network in the ATM network. A cell multiplexer which functions as cell buffer, and also serves as multiplexer and demultiplexer. A router which controls VPI/VCI (Virtual Path Identifier/Virtual Channel Identifier) of ATM cell at the routing table according to path, and sends the VPI/VCI value which is the result path of the link, to the header of ATM cell. A buffer which receives ATM cell stream from the router for storage, and at the request of SSU (STARacer Switching Unit) which performs cell-switching at the ATM network system, provides the stored ATM cell stream. A central processing unit (CPU) module which works with SPU (STARacer Processing Unit) connected to ATM network and NMS (Network Management System). An address/data decoder which interfaces with the CPU module according to the address region and data region depending on each input/output devices. An interrupt controller which assigns interrupt priority to the input/output devices of prepared cycle, and controls the interrupt which is sent to the CPU module. A bus controller which interfaces with each input/output devices according to 8, 16, and 32 bit data bus types. A bus arbitrator which controls the right to use buses between the CPU module and an Ethernet controller. An Ethernet controller which supports IPC (Inter-Process Communication) in the ATM network. A clock controller which extracts and processes clock synchronization information of PDH data stream contained in the cell stream of the ATM network; and a system clock distributor which receives a system clock of 50 MHz and 8 KHz, and divides the system clock to the input/output devices.
The present invention is more specifically described in the following paragraphs by reference to the drawings attached only by way of example.